An active-matrix type display device displays an image by selecting pixel circuits arranged two-dimensionally in unit of row and writing voltages in accordance with image data to the selected pixel circuits. In order to select the pixel circuits in unit of row, a shift register for sequentially shifting an output signal based on a clock signal is used as a scanning line drive circuit. Furthermore, in a display device for performing a dot sequential drive, a similar shift register is provided inside a data line drive circuit.
In a liquid crystal display device or the like, a drive circuit of the pixel circuits may be formed integrally with the pixel circuits using a manufacturing process for forming a TFT (Thin Film Transistor) in the pixel circuit. In this case, in order to reduce a manufacturing cost, it is preferable to form the drive circuit including the shift register with transistors having a same conductive type as the TFT.
Regarding the shift register, various circuits are conventionally known. For example, Patent Document 1 describes a shift register in which unit circuits 901 shown in FIG. 38 are connected in multi-stage. The shift register performs a normal operation when an all-on control signal AON is at a low level and a negative signal AONB of the all-on control signal is at a high level. At this time, transistors Q21, Q23, Q24 turn off and a transistor Q22 turns on.
The normal operation of the unit circuit 901 will be described below. At first, when an input signal IN changes to the high level, a transistor Q1 turns on, a potential of a node N1 is increased to (VDD−Vth) (Vth is a threshold voltage of the TFT), the node N1 becomes a floating state, and transistors Q2, Q31 turn on. Since a clock signal CK is at the low level at this time, output signals OUT1, OUT2 are at the low level. Furthermore, when the input signal IN changes to the high level, a transistor Q7 turns on, and a potential of a node N2 becomes the low level. Next, when the input signal IN changes to the low level, the transistors Q1, Q7 turn off.
Next, when the clock signal CK changes to the high level, the output signals OUT1, OUT2 become the high level. At this time, the potential of the node N1 is pushed up via a capacitor C1 and parasitic capacitance of the transistors Q2, Q31, and the potential of the node N1 becomes higher than (VDD+Vth) Thus, potentials of the output signals OUT1, OUT2 become VDD. Next, when the clock signal CK changes to the low level, the potential of the node N1 returns to (VDD−Vth) and the output signals OUT1, OUT2 become the low level.
Next, when a clock signal CKB changes to the high level, a transistor Q6 turns on, the potential of the node N2 is increased to (VDD−Vth), and the node N2 becomes the floating state. Thus, transistors Q3, Q4, Q32 turn on and the potential of the node N1 becomes the low level. Next, when the clock signal CKB changes to the low level, the transistor Q6 turns off.
After that, the clock signal CKB becomes the high level and the low level in a predetermined cycle. In a high level period of the clock signal CKB, the transistor Q6 turns on and a high level potential is applied to the node N2. In a low level period of the clock signal CKB, the transistor Q6 turns off and the node N2 keeps the high level potential in the floating state.
When the all-on control signal AON is at the high level and the negative signal AONB of the all-on control signal is at the low level, the shift register performs an operation (hereinafter referred to as all-on output) for setting all of the output signal OUT1 to an on level (a level at which transistor turns on). At this time, the transistors Q21, Q23, Q24 turn on and the transistor Q22 turns off. Thus, the potential of the node N2 becomes the high level, the transistors Q4, Q32 turn on, the potential of the node N1 becomes the low level, and the transistors Q2, Q31 turn off. Furthermore, since a gate potential of the transistor Q3 becomes the low level, the transistor Q3 turns off. In this manner, since the transistors Q2, Q3 turn off and the transistor Q24 turns on, the output signal OUT1 becomes the high level. On the other hand, since the transistor Q31 turns off and the transistor Q32 turns on, the output signal OUT2 becomes the low level.
In a display device (refer to FIG. 35 described later) including the shift register as the scanning line drive circuit, the shift register performs the all-on output, for example, when a power is turned on or off. With this, it is possible to select all of the scanning lines collectively, turn on write control transistors included in all of the pixel circuits in a display area, and discharge charge accumulated in the pixel circuits to data lines. Furthermore, the shift register performs the all-on output when testing a display panel. With this, it is possible to turn on the write control transistors included in all of the pixel circuits in the display area, and write a check voltage to all of the pixel circuits collectively.
Related to the invention of this application, Patent Document 2 describes providing, to a unit circuit of a shift register, an initialization transistor having one end connected to a control terminal of an output transistor and a control terminal to which an initialization signal is supplied, and connecting the other end of the initialization transistor to a node which has an off potential when performing an initialization and has an on potential of a same level as a clock signal when the clock signal having the on potential is output.